All-around encapsulated Xene membranes for integration in transistors

Introduction

Silicon is the key building block of transistors, the workhorse of modern electronics. Since the early 2000s, scaling down the transistors' size according to Moore's Law to increase clock speed, decrease energy requirements, and enhance compactness has been progressively more challenging than it had been for the previous 40 years.

Technological Vision

Reducing silicon at the two-dimensional level is a technological vision to achieve the ultimate shrinking of high-performance electronic devices. This approach aims to gain enough mechanical flexibility to make it integrable in low-power flexible devices.

Proposed Solution

We propose to attain this breakthrough result by stabilizing silicene, an atomically thin silicon layer with a nearly graphene-like structure, by physically protecting both of its faces. Our goal is the scalable production of durable silicene in the form of atomically thin membranes.

Production and Integration

Standardized production of silicene membranes will be assessed for integration into:

1. High-performance transistors
2. Low-power and flexible transistors

These transistors will have unprecedented outperforming technical advantages, including:

• Intrinsic channel miniaturization
• High carrier mobility
• High energy efficiency
• Large-scale uniformity
• High flexibility
• Transfer compatibility with secondary substrates

Additionally, there will be a substantial reduction in energy consumption.

Sustainability Impact

These characteristics make silicene membranes a promising component of sustainable electronics for massive diffused societal trends like the Internet of Things.

Project Goals

The goal of this PoC project is to validate with industrial players the technological feasibility of a prototypal silicene-based transistor, while simultaneously defining the best IP protection and commercialization route.