igzO-based smaRt Interposer technologieS fOr iNtegrated circuits and pixels

Introduction

Silicon complementary metal-oxide semiconductor (Si CMOS) technologies are ubiquitous in a plethora of products today employing a multitude of chips. The current challenges of Si chips research and applications are area, power consumption, and high-voltage interposing for AR/VR, low-power IoT, high-voltage sensors, and actuator interfaces such as MEMS and lab-on-chip.

Project Goals

ORISON’s goal is to develop a scalable toolbox on top of Si CMOS chip technologies for disruptive research activities in:

1. Ultralow power circuit design
2. High-voltage interfacing
3. Low-area 3D stacked hybrid pixel engines

The technology platform focuses on a 3D hetero-integration route of Si CMOS and Indium-Gallium-Zinc-Oxide (IGZO) n-type transistors with a 100x lower electron mobility. The game-changing nature of ORISON enables innovation on three major pillars:

1. Extreme low off-stage leakage currents due to the wide bandgap semiconductor, leading to ultralow power and long retention electronic circuits.
2. The absence of a bulk for IGZO devices, enabling low footprint and high-voltage devices on top of Si CMOS.
3. A 3D technology platform facilitating beyond state-of-the-art circuit and pixel resolutions.

Hybrid Cell Library Development

A new hybrid Si pMOS/IGZO cell library will be pioneered targeting ultra-low power consumption because of:

• Comparable sub-threshold slopes of both technologies
• Low off-state leakage currents
• Individual tunable threshold voltages by a local backgate

In addition, true cell-level power gating techniques are envisioned to radically reduce idle power consumption, paving the way to lifetime battery-powered or battery-less wearables and leaf-node IoT.

Impact on Applications

The novel high-voltage hybrid library positively impacts MEMS and AR/VR applications with unprecedented footprint and power characteristics and enables technology partitioning for smart pixels. The 3D technology also envisions high-resolution pixel engines with refresh-on-demand capacitor-less pixel engines.