Ultralow-power logic-in-memory devices based on ferroelectric two-dimensional electron gases

Introduction

Microelectronics components are at the core of our modern economies. The corresponding global market is exponentially growing at an annual pace of 10-15% and should reach the trillion $ by 2030.

Technological Framework

The techno-economic framework that has been driving this industry is based on:

• Boolean logic
• von Neumann architectures (with separated computing and memory units)
• CMOS transistors

It is pictured by the famous Moore's law, describing the continuous shrinking of transistor size. For years, Dennard's scaling law of power consumption provided a path to shrinking such transistors while keeping the power density constant.

Current Challenges

However, as technological nodes become today as small as tens of atoms, we are hitting fundamental limits, leading to heating and preventing this downscaling. Simultaneously, the power consumption of information and communication technologies (ICT) represents nearly 5% of the world's energy consumption.

Need for Innovation

To mitigate these civilizational issues, new devices and architectures for ICT must be invented. The consensus reached by the microelectronics community is that to reduce power consumption:

1. Memory and logic units must be brought together
2. The inherent nonvolatile properties of ferroic materials are a valuable asset to avoid static power consumption.

Project Overview

UPLIFT proposes to develop the proof of concept (POC) of a non-volatile, spin-based, ultralow power (aJ) logic-in-memory component, coined FESO, which harnesses the ferroelectric control of spin-charge interconversion discovered within the ERC FRESCO.

Technical Goals

We will pattern devices down to the 100 nm scale and aim for:

• 100 mV output voltages
• 1 ns operation speed
• Endurance > 10^9 cycles

Commercial Exploitation

UPLIFT will benefit from a well-defined path towards commercial exploitation, including a decade-long collaboration between the Principal Investigator (PI) and two researchers from Spintec in Grenoble. Together, they are launching a start-up company that will exploit the patent portfolio filed within FRESCO.

Future Prospects

This POC project will serve both as support and a propeller for the start-up, to be created in Q1 2024.