On-chip waste recovery in quantum and nanoscale devices guided by novel performance quantifiers

Introduction

Quantum and nanoscale technologies promise to revolutionise computing, sensing, information, and communication applications. However, they are missing a dedicated effort towards energy sustainability by exploiting their characteristic properties.

Project Overview

The theoretical project NanoRecycle addresses this important outstanding problem by developing schemes for on-chip recovery of waste that typical device operations leave behind. In classical devices, this waste is often dissipated heat, but waste in nanoscale and quantum devices has characteristic nonthermal, fluctuating, and quantum properties.

Objectives

The scope of NanoRecycle is to develop processes that convert this waste into electrical power or other resources that are useful for further on-chip tasks. The analysis will be based on sufficiently generic setups to capture the characteristic waste properties, which are:

1. Typical elements of current quantum and nanotechnologies.
2. Concretely connected to feasible, state-of-the-art experiments.

This involves multi-terminal electronic conductors, as well as hybrid devices coupling to microwave resonators.

Methodology

To guide the design, analysis, and optimisation of on-chip waste recovery, my team and I will first capture and quantify the characteristic properties of the various types of waste. We will then establish comprehensive performance quantifiers for the efficiency of dedicated conversion processes.

Performance Goals

An important performance goal of such a conversion in small-scale devices, which we will also account for in our performance analysis, is the output power precision. This refers to the suppression of power fluctuations, which is crucial for further on-chip use.

Conclusion

While the power obtained from this waste recovery is expected to be small, its potential for contributing to energy-sustainable processes lies in the availability on-chip for further use. This approach circumvents high-loss attenuation procedures that occur when bringing large classical fields down to the chip.